研究目的
Investigating the design and performance of a voltage controlled delay buffer using a 2:1 multiplexer in 0.35 μm CMOS process for high speed, low power, and full swing output characteristics.
研究成果
The multiplexer based delay buffer element realized by transmission gate achieves a least propagation delay of 120 ps, zero static current, and 1.4ms dynamic current with full output swing from 0 to 3.3 V. Its performance against PVT variations is successfully verified with a designed modified DLL with loop control in single (rising) edge delay.
研究不足
The design's performance is limited by the 0.35 μm CMOS process technology used, which may affect the achievable resolution and speed compared to more advanced process technologies.
