研究目的
Investigating the influence of the variations of QD dimensions on the performance of hybrid SET-FET circuits.
研究成果
The variation of the QD size presents the largest influence on the overall circuit behavior of hybrid SET-FET circuits. The introduction of an additional voltage source at the source terminal of the FET device can improve circuit performance by increasing the output current.
研究不足
The compact model's accuracy is reduced for QD sizes below 5 nm, and it overestimates the effective bandgap of the QD. The model also has limitations in describing the SET characteristics for drain voltages above 100 mV.
1：Experimental Design and Method Selection:
The study employs a self-developed SET compact model calibrated to 3-D quantum-mechanics-based simulations to analyze the impact of QD variations on hybrid SET-FET circuits.
2：Sample Selection and Data Sources:
The analysis is based on simulations of vertical nanowire SETs with embedded silicon QDs.
3：List of Experimental Equipment and Materials:
The simulations utilize a commercial Schroedinger/Poisson solver (nextnano++) for 3-D quantum-mechanics-based simulations.
4：Experimental Procedures and Operational Workflow:
The study involves varying QD dimensions and positions, and analyzing their impact on SET and SET-FET circuit performance through simulations.
5：Data Analysis Methods:
The impact of QD variations is evaluated using statistical distributions to determine device variation ratios.
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