研究目的
Investigating the design and performance of an ultra-low-voltage, high-speed pipeline ADC using dynamic amplifiers.
研究成果
The paper demonstrates the feasibility of ultra-low voltage high-speed analog circuit design through the combination of interpolated pipeline architecture and dynamic residue amplifiers. A 7-bit prototype ADC achieves a conversion rate of 160 MS/s with a supply voltage of 0.55 V, showcasing the potential for energy-efficient systems in scaled CMOS technologies.
研究不足
The dynamic amplifiers in this design are unable to maintain a sufficiently high gain at high temperatures due to the decrease of transconductance, which leads to a higher common-mode voltage and compromised gain. A potential solution to compensate for this is to maintain a constant common-mode voltage in the background, but this design does not incorporate such a calibration technique.
1：Experimental Design and Method Selection:
The paper presents a pipeline ADC design using dynamic amplifiers with a common-mode detection technique for high-speed operation and robustness against supply voltage scaling. The interpolated pipeline architecture is employed to shift the gain requirement from absolute to relative accuracy between a pair of residue amplifiers.
2：Sample Selection and Data Sources:
The prototype ADC is fabricated in 90 nm CMOS technology with low threshold voltage and deep N-well options.
3：List of Experimental Equipment and Materials:
The ADC uses dynamic amplifiers, interpolation capacitor arrays, and a pseudo-static resistive DAC for common-mode voltage calibration.
4：Experimental Procedures and Operational Workflow:
The ADC operates with a self-clocking scheme, utilizing dynamic amplifiers and comparators to self-allocate timing, eliminating the need for a conventional clock tree.
5：Data Analysis Methods:
The performance of the ADC is evaluated based on its effective number of bits (ENOB), signal-to-noise and distortion ratio (SNDR), and figure-of-merit (FoM).
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