研究目的
Exploring full atomic-layer-deposition Al2O3/ZrO2/SiO2/ZrO2/Al2O3 stacks for high-performance MIM capacitors to meet the requirement of high capacitance density and improved voltage linearity.
研究成果
The MIM capacitor with 3 nm SiO2 in the AZSZA stack exhibits desirable characteristics such as a capacitance density of 7.40 fF/μm2, improved voltage linearity (α of ?121 ppm/V2, β of ?116 ppm/V), extremely low leakage current, high breakdown field, and robust reliability, making it a promising candidate for RF and AMS ICs.
研究不足
The study focuses on the optimization of SiO2 thickness within the AZSZA stack for improved voltage linearity and capacitance density, but does not explore the impact of other dielectric materials or stack configurations.
1：Experimental Design and Method Selection:
Various AZSZA stacks were assembled by ALD in the same chamber without vacuum interruption. The thicknesses of individual Al2O3 and ZrO2 layers were optimized at 1 nm and 7 nm, respectively. Different thicknesses of SiO2 (0, 1, 2 and 3 nm) were incorporated to study how the SiO2 layer thickness modulated α value.
2：Sample Selection and Data Sources:
The MIM capacitors were fabricated atop a sputtered TaN bottom electrode deposited on a 500 nm PECVD-SiO2 film.
3：List of Experimental Equipment and Materials:
ALD system for dielectric deposition, sputtering system for electrode deposition, precision impedance analyzer (Agilent 4294A), semiconductor device analyzer (Agilent B1500A), ellipsometer, transmission electron microscopy (TEM).
4：Experimental Procedures and Operational Workflow:
The MIM capacitors were defined by photolithography and dry etching, followed by annealing in a rapid thermal annealing (RTA) system at 420 °C for 5 min in forming gas.
5：Data Analysis Methods:
Capacitance–voltage (C–V) and current-voltage (I–V) measurements were carried out to extract VCCs and leakage current densities.
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