研究目的
To propose a novel implementation of a complex analog equalization filter for the compensation of frequency-dependent variations in coherent optical links, aiming to limit the complexity and power consumption by removing digital signal processing (DSP).
研究成果
The designed analog FIR filter shows promising results for compensating frequency-dependent variations in coherent optical links, with a core power consumption of 185 mW from a 2.5-V supply. The chip's functionality is successfully verified, demonstrating its potential as a low-complexity alternative to DSP filtering in future applications.
研究不足
The study is limited by the technology used (55-nm BiCMOS) and the specific application in coherent optical links. The noise introduced by the equalizer chip and the limited bandwidth of the last taps in the filter are noted as areas for optimization.
1：Experimental Design and Method Selection:
The study employs a distributed FIR filter architecture with custom-designed analog delay circuits and Gilbert cell multipliers to control the filter transfer function.
2：Sample Selection and Data Sources:
The chip is fabricated in a 55-nm BiCMOS technology and tested with 28-GBd 16-QAM modulation.
3：List of Experimental Equipment and Materials:
A four-port vector network analyzer (VNA), a 92-GS/s arbitrary waveform generator (AWG), and a real-time oscilloscope (RTO) are used for measurements.
4：Experimental Procedures and Operational Workflow:
The chip's functionality is verified via S-parameter measurements and system experiments. The waveforms are analyzed in software to calculate updates for the equalizer taps.
5：Data Analysis Methods:
The performance is evaluated using S-parameter measurements, noise and linearity measurements, and real-time system experiments.
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