研究目的
To address the challenge of real-time analysis of single-photon coincidence in photonic quantum computing by proposing a real-time time-tagged coincidence method and a data filtering solution.
研究成果
The developed 32-channel CCU implemented on the COINS6 module provides high counting rates, a tunable coincidence window, and a timing resolution of 390 ps. It is feasible to scale up to 104 channels, making it suitable for applications like boson sampling. Future work includes addressing jitter issues and expanding the CCU to 104 channels.
研究不足
The study notes that large jitters may lead to errors in the coincidence process, especially as the channel number scales up. Improvements are suggested, such as increasing the backplane frequency bandwidth and applying differential routings from I/O boards to the COINS6 board.
1：Experimental Design and Method Selection:
The study employs a real-time time-tagged coincidence method and a data filtering solution, implemented on a field-programmable gate array (FPGA) system.
2：Sample Selection and Data Sources:
The experiment uses a 32-channel coincidence counting unit to demonstrate the method's effectiveness.
3：List of Experimental Equipment and Materials:
The COINS6 module, a printed circuit board containing a Spartan-6 FPGA, and peripherals including a USB
4：0 port and I/O boards. Experimental Procedures and Operational Workflow:
The TDCs provide timestamps for the window comparators to generate coincidence code words, which are used to address memory on-chip or output directly via USB.
5：Data Analysis Methods:
The study includes a code-density test to measure the non-uniformity of time-bins and a test to measure the width of the coincidence time window.
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Tektronix AFG 3252
AFG 3252
Tektronix
Generates an 80 MHz clock as the TDC clock source for testing.
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Agilent 81134A pulse generator
81134A
Agilent
Outputs an 80 MHz pseudo random binary sequence (PRBS) as a test signal.
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Agilent 91204 digital oscilloscope
91204
Agilent
Measures the time interval error (TIE) against the reference clock provided by the 81134A.
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Agilent 81150 AFG
81150
Agilent
Generates uncorrelated clock as hit signals for testing.
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COINS6 module
XC6SLX16CSG324-2
Xilinx
Provides an infrastructure for the CCU framework, including a Spartan-6 FPGA and peripherals.
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LEMO connector
LEMO
Used for trigger applications and signal flow direction indication.
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USB 2.0 port
Used for configuration, monitoring, and data readout.
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DDR memory
MT46H64M16LFCK-5
Micron Technology
Accessible by the FPGA for additional memory needs.
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