研究目的
To study the parasitic capacitance of tapered through silicon via (T-TSV) with respect to thermal properties and propose the Temperature Coefficient of Capacitance (TCC) to model the sensitivity of TSV capacitance to temperature.
研究成果
The TCC concept effectively models the temperature sensitivity of TSV capacitance, showing that TCC increases with temperature and is influenced by TSV dimensions. Cylindrical TSVs are more thermally stable than tapered ones. This provides a basis for designing TSVs with improved thermal performance in 3D ICs.
研究不足
The study is based on analytical models and does not include experimental validation or measurements. It assumes specific fixed parameters (e.g., doping concentration, material properties) and may not account for all real-world variations or manufacturing imperfections.
1：Experimental Design and Method Selection:
The study uses analytical modeling based on semiconductor physics equations to derive the Temperature Coefficient of Capacitance (TCC) for tapered TSVs, incorporating MOS capacitance effects.
2：Sample Selection and Data Sources:
The analysis is theoretical, using fixed parameters such as p-doping concentration Na =
3：25e15 cm^-3, TSV radius Rtsv = 5 μm, height h = 50 μm, dielectric thickness tdie = 1 μm, and temperature range from 300 K to 500 K. List of Experimental Equipment and Materials:
No specific equipment or materials are mentioned; the study is computational.
4：Experimental Procedures and Operational Workflow:
Equations are derived and solved to compute Ctsv and TCC as functions of temperature and TSV dimensions (e.g., radius, dielectric thickness, slope angle).
5：Data Analysis Methods:
Analytical calculations and graphical analysis (e.g., plots of Ctsv vs. temperature, TCC vs. temperature) are used to interpret results.
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