研究目的
To achieve monolithic integration of silicon ribbon (SiRi) sensors with CMOS circuits for selective and multiplexed detection in lab-on-chip applications, addressing the challenge of real-time signal detection and compact sensor design.
研究成果
The monolithic integration of SiRi sensors with CMOS using a pixel-based architecture is successfully demonstrated, enabling selective and multiplexed detection. P-type pixels show excellent performance with high ION/IOFF ratios and low subthreshold slopes, while N-type pixels face limitations due to high backgate voltage requirements. The findings support large-scale, cost-effective production of lab-on-chip sensors, with recommendations for future work to optimize the backgate interface and reduce operating voltages.
研究不足
The study is limited by the high threshold voltage variations due to the thick buried oxide layer (145 nm) in the SOI wafer, which requires large backgate voltages (e.g., ≥25 V for N-type) and can prevent the pixels from turning off. The quality of the backgate interface and fixed charges in the oxide impact performance, and the fabrication process may introduce variations. Additionally, the work focuses on electrical characterization prior to bio-functionalization, so actual biosensing applications are not demonstrated.
1：Experimental Design and Method Selection:
The study employs a top-down fabrication method on a silicon-on-insulator (SOI) wafer to create SiRi pixel sensors integrated with CMOS transistors. Each pixel includes a control FET, fluid gate, and SiRi sensor, operated in frontgate and backgate modes for electrical characterization.
2：Sample Selection and Data Sources:
Boron-doped 4-inch SOI wafers with a 145 nm buried oxide layer and 55 nm crystalline silicon device layer are used. Samples include N-type and P-type SiRi pixels with specific dimensions (e.g., SiRi: 1 μm x 1 μm x 20 nm; control transistor: 4 μm x 1 μm).
3：List of Experimental Equipment and Materials:
Equipment includes a Cascade 12,000 semi-automatic wafer prober, Keithley 4200-SCS parameter analyzer, plasma-enhanced chemical vapor deposition (PECVD) system, reactive ion etching (RIE) chamber, atomic layer deposition (ALD) system, and scanning electron microscope (SEM). Materials include SOI wafers, SiO2, TiN, polysilicon, Ni, TiW, Al, and various gases for etching and deposition.
4：Experimental Procedures and Operational Workflow:
Fabrication involves thermal oxidation, lithography, etching, ion implantation, metallization, and passivation. Electrical measurements are performed using DC characterization with voltage sweeps for frontgate and backgate modes to obtain transfer characteristics (ID-VG and ID-VBG).
5：Data Analysis Methods:
Data is analyzed using linear extrapolation to extract threshold voltage (VTH) and subthreshold slope (SS). Wafer-scale mapping and statistical analysis of performance metrics (e.g., ION/IOFF ratio) are conducted.
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