研究目的
To present new current-mode compressors (Binary Converters) based on CNTFET technology for efficient multiplication operations in VLSI circuits.
研究成果
The paper concludes that CNTFET-based designs offer superior performance over MOSFET, with the second approach (using only 4BCs and HAs) providing faster computation and fewer transistors in multipliers, highlighting the efficiency of lower-input BCs.
研究不足
High-order BCs suffer from longer delay and higher power consumption; precise fabrication of CNT diameters is challenging, affecting threshold detector accuracy; noise margin reduces with more voltage levels; static power dissipation is an issue in CML.
1：Experimental Design and Method Selection:
The study designs new Binary Converters (BCs) using CNTFET technology, with two approaches: one using high-order BCs and another using only 4BCs and Half Adders. Theoretical models include current-mode logic and redundant numeral systems.
2：Sample Selection and Data Sources:
Simulations are performed using standard 32nm CNTFET technology models from Stanford University.
3：List of Experimental Equipment and Materials:
Synopsys HSPICE simulator, CNTFET models, MOSFET models for comparison.
4：Experimental Procedures and Operational Workflow:
Circuits are designed and simulated in HSPICE at 1V power supply and 1GHz frequency; performance metrics (delay, power, PDP) are measured; an 8×8-bit multiplier is used as a benchmark.
5：Data Analysis Methods:
Performance is evaluated using Power-Delay Product (PDP) and comparison with MOSFET-based designs.
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