1：Experimental Design and Method Selection:

The study compares two workflows: a pure HDL (VHDL) implementation and an HLS-based implementation using Vivado HLS. The designs are for image processing accelerators focusing on Grayscale conversion and Sobel Edge Detection algorithms. The VHDL design was simulated and synthesized using Altera's Quartus, while the HLS design used Xilinx Vivado HLS to generate VHDL from C++ code.

2：Sample Selection and Data Sources:

The input set consisted of 50 images in 640x480 BMP uncompressed format. Images were processed to evaluate performance and quality metrics such as PSNR.

3：List of Experimental Equipment and Materials:

Equipment includes Altera DE2-115 Cyclone IV E FPGA board, Xilinx Pynq-Z1 board, workstation with Intel Core i5-4460 CPU, 16 GB RAM, running Windows

4：Software tools:

Altera Quartus 15.0, Vivado HLS, Python libraries for Pynq-Z

5：0, Vivado HLS, Python libraries for Pynq-ZExperimental Procedures and Operational Workflow:

1. 4. Experimental Procedures and Operational Workflow: For the VHDL design, images were transferred via USB to the FPGA, processed using custom VHDL modules, and results displayed. For the HLS design, images were processed using Python overlays on the Pynq-Z1 board with AXI DMA for data transfer. Processing times and quality metrics were measured and compared.

6：Data Analysis Methods:

Data analysis included calculating Mean Square Error (MSE) and Peak Signal-to-Noise Ratio (PSNR) to compare image quality. Processing times were measured and normalized for clock speed comparisons. Resource utilization and power consumption were analyzed from synthesis reports.