研究目的
To demonstrate negative capacitance transistors based on black phosphorus for achieving steeper subthreshold slopes, which are beneficial for low-voltage and low-power circuit applications.
研究成果
The demonstration of BP NC-FETs shows significant reduction in subthreshold slope, down to 104 mV/dec, validated by a theoretical model. This work highlights the potential of BP-based negative capacitance transistors for low-power flexible electronics, with suggestions for future optimization to minimize hysteresis and improve performance.
研究不足
The hysteresis in the devices due to interface trapping and charge effects, which can screen the ferroelectric polarization and affect performance. The SS achieved is not a record low compared to some other technologies, and the devices may have issues with oxidation of BP in air.
1:Experimental Design and Method Selection:
The study fabricated two types of BP NC-FETs by connecting regular BP FETs to a negative capacitance capacitor made of HfZrO ferroelectric material. This approach was chosen to avoid interface effects and allow separate optimization of the FET and capacitor. Theoretical modeling based on the Landau-Khalatnikov equation and Poisson's equation was used to analyze the NC effect.
2:Sample Selection and Data Sources:
BP flakes were exfoliated on SiO2 substrates. The devices were fabricated and characterized electrically.
3:List of Experimental Equipment and Materials:
Atomic layer deposition (ALD) system for depositing AlOx and HfZrO films, e-beam lithography system for patterning, thermal evaporation system for metal deposition, sputtering system for TiN electrodes, transmission electron microscope (TEM) for imaging, and electrical measurement setups for polarization, capacitance, and transistor performance.
4:Experimental Procedures and Operational Workflow:
For type-I BP FET: exfoliate BP on SiO2, pattern source/drain contacts via e-beam lithography and thermal evaporation, deposit 30-nm AlOx by ALD, form top-gate electrode. For type-II BP FET: form Al metal on BP to self-form 5-nm AlOx, then exfoliate BP and form source/drain. For NC capacitor: sputter TiN bottom gate, deposit 20-nm HfZrO by ALD, deposit and pattern top TiN electrode, anneal. Connect FET to capacitor and measure electrical properties.
5:Data Analysis Methods:
Polarization measured using positive up negative down method, capacitance measured with small signal method, subthreshold slope extracted from transfer curves, and theoretical model fitted to experimental data using Landau coefficients.
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Atomic Layer Deposition System
Not specified
Not specified
Used for depositing AlOx and HfZrO films in the fabrication process.
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E-beam Lithography System
Not specified
Not specified
Used for patterning source/drain contacts and gate electrodes.
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Thermal Evaporation System
Not specified
Not specified
Used for depositing metal contacts such as Cr and Au.
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Sputtering System
Not specified
Not specified
Used for depositing TiN electrodes.
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Transmission Electron Microscope
Not specified
Not specified
Used for imaging the TiN/HZO/TiN sandwich structure.
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HfZrO Ferroelectric Capacitor
20-nm thickness
Not specified
Provides negative capacitance to reduce subthreshold slope in transistors.
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AlOx Gate Dielectric
30-nm and 5-nm thicknesses
Not specified
Used as gate dielectric in the BP FETs.
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