1：Experimental Design and Method Selection:

The study involved designing and fabricating fully-vertical GaN-on-Si MOSFETs using a robust process that includes selective removal of the Si substrate and resistive buffer layers, conformal copper electroplating for mechanical stability and electrical contact, and optimization of gate trench fabrication to enhance channel mobility and output current. Theoretical models for mobility extraction and device performance benchmarking were employed.

2：Sample Selection and Data Sources:

The devices were fabricated on a 6.6 μm-thick n-p-i-n GaN epitaxial structure grown on a 6-inch Si (111) substrate by MOCVD. The epitaxial layers included buffer, n-GaN, i-GaN, p-GaN, and n+-GaN layers with specified doping concentrations.

3：6 μm-thick n-p-i-n GaN epitaxial structure grown on a 6-inch Si (111) substrate by MOCVD. The epitaxial layers included buffer, n-GaN, i-GaN, p-GaN, and n+-GaN layers with specified doping concentrations. List of Experimental Equipment and Materials:

3. List of Experimental Equipment and Materials: Equipment included MOCVD system for epitaxial growth, dry-etching tools (e.g., Cl2-based for mesa and trench etching), atomic layer deposition (ALD) for SiO2 gate oxide, e-beam evaporator for metal deposition, electroplating setup for copper deposition, rapid thermal anneal (RTA) furnace, SEM for imaging, and electrical measurement setups. Materials included GaN epitaxial layers, Si substrate, Ni and SiO2 hard masks, TMAH for surface treatment, Cr/Au for contacts, copper for electroplating, and QuickStick 135 mounting wax.

4：Experimental Procedures and Operational Workflow:

The fabrication steps involved: dry-etching of gate trench using metal (Ni) or oxide (SiO2) hard masks, TMAH wet treatment at 85°C for 1 hour to smoothen sidewalls, RTA at 750°C for 20 min in N2 to activate p-GaN, mesa isolation etch, ALD of SiO2 gate oxide, source contact opening, Cr/Au deposition for gate and source contacts, Si substrate thinning, attachment to support wafer with QuickStick 135, backside patterning, dry-etching of Si substrate and buffer layers, Cr/Au deposition for drain contact, electroplating of 35-μm-thick copper layer, and release from support wafer. Electrical characterization included IDS-VDS, IDS-VGS, transconductance, mobility extraction, and breakdown voltage measurements.

5：Data Analysis Methods:

Data were analyzed using standard semiconductor device characterization techniques. Field-effect mobility was extracted from transconductance measurements using the relation gm = (Z/L)×μ×Co×VDS. Specific on-resistance and breakdown voltage were calculated from current-voltage characteristics. Comparisons were made with quasi-vertical devices and other reported GaN transistors.