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[IEEE 2018 2nd International Conference on Trends in Electronics and Informatics (ICOEI) - Tirunelveli, India (2018.5.11-2018.5.12)] 2018 2nd International Conference on Trends in Electronics and Informatics (ICOEI) - FPGA Implementation of Energy Efficient Approximate Multiplier with Image Processing Applications
摘要： Multiplication is the pivotal building squares in image processing, DSP applications. To make high-speed here using an approximate multiplier this is an efficient one. For that the method is to rounding the values of numbers to the nearest power of two. Using this method the complicated part of multiplication can be removed thus can improve the speed of multiplication. This multiplier is applicable for both positive and negative number. The efficiency of this multiplier is analysed by comparing with the accurate multipliers and finally studied its efficiency image image processing applications smoothening and sharpening. The multiplier operation is finally implemented in FPGA SPARTAN kit.
关键词： smoothening,FPGA,sharpening,SPARTAN,approximate
更新于2025-09-09 09:28:46
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[IEEE 2017 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC) - Atlanta, GA (2017.10.21-2017.10.28)] 2017 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC) - Design of a 2-Bit Sigma-Delta Modulator for Scintillation Waveform Capture
摘要： Sigma-delta modulation is a common technique used in analog-to-digital conversion. It has been shown that it can be implemented in a field-programmable gate array (FPGA) using minimal external analog components. Zhao et al. demonstrated that energy of scintillation pulses can be computed by adding up all the elements on the output from a conventional 1-bit sigma-delta modulator. However, for parameters selected for a suitable resolution and dynamic range, the system passes through a period of saturation. During saturation, information about the shape of the pulse is lost even though the integrated energy remains preserved. We present the design of a 2-bit version of the sigma-delta modulator that makes use of a nonlinear adaptive digital-to-analog converter (DAC) that keeps the system unsaturated. Each output bit is scaled by one of the four possible values the DAC can take, resulting in a 2-bit modulation. We have demonstrated that the 2-bit modulation retains information about the pulse shape.
关键词： Sigma-delta modulation,analog-to-digital conversion,FPGA,scintillation waveform capture,digital-to-analog converter
更新于2025-09-09 09:28:46
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HW/SW co-design of a visual SLAM application
摘要： Vision-based advanced driver assistance systems (ADAS), appeared in the 2000s, are increasingly integrated on-board mass-produced vehicles, as off-the-shelf low-cost cameras are now available. But ADAS implement most of the time-specific and basic functionalities such as lane departure or control of the distance to other vehicles. Integrating accurate localization and mapping functionalities meeting the constraints of ADAS (high-throughput, low-consumption, and small-design footprint) would pave the way towards obstacle detection, identification and tracking on-board vehicles at potential high speed. While the SLAM problem has been widely addressed by the robotics community, very few embedded operational implementations can be found, and they do not meet the ADAS-related constraints. In this paper, we implement the first 3D monocular EKF-SLAM chain on a heterogeneous architecture, on a single System on Chip (SoC), meeting these constraints. In order to do so, we picked up a standard co-design method (Shaout et al. Specification and modeling of hw/sw co-design for heterogeneous embedded systems, 2009) and adapted it to the implementation of potentially any of such complex processing chains. The refined method encompasses a hardware-in-the-loop approach allowing to progressively integrate hardware accelerators on the basis of a systematic rule. We also have designed original hardware accelerators for all the image processing functions involved, and for some algebraic operations involved in the filtering process.
关键词： SLAM,ADAS,FPGA,Co-design,Machine-vision
更新于2025-09-09 09:28:46
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An FPGA-based quantum circuit emulation framework using heisenberg representation
摘要： While physical realization of practical large-scale quantum computers is still ongoing, theoretical research of quantum computing applications is facilitated on classical computing platforms through simulation and emulation methods. Nevertheless, the exponential increase in resource requirement with the increase in the number of qubits is an inherent issue in classical modeling of quantum systems. In the e?ort to alleviate the critical scalability issue in existing FPGA emulation works, a novel FPGA-based quantum circuit emulation framework based on Heisenberg representation is proposed in this paper. Unlike previous works that are restricted to the emulations of quantum circuits of small qubit sizes, the proposed FPGA emulation framework can scale-up to 120-qubit on Altera Stratix IV FPGA for the stabilizer circuit case study while providing notable speed-up over the equivalent simulation model.
关键词： stabilizer circuit,quantum Fourier transform,FPGA emulation,Heisenberg representation
更新于2025-09-09 09:28:46
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[IEEE 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI) - Bangalore, India (2018.9.19-2018.9.22)] 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI) - FPGA based Ultrasonic thickness measuring device
摘要： This paper aims at the development of ultrasound based thickness measurement device. A Spartan 6 FPGA from Xilinx has been used in the hardware design along with external parallel Analog to Digital and digital to Analog converter. The device is interfaced with a PC or laptop through USB cable. A measurement and control software is developed using MATLAB for conceptual level and final Graphical User Interface has been developed in .NET to transfer different user defined control parameters to the hardware and receive the captured signal. Ultrasonic probes are used to generate and receive physical sound wave in pulse-echo mode. Time of flight (ToF) based calculations are used for deriving the subject dimension.
关键词： ADC Module,Contact Transducer,DAC Module,NDT,Ultrasonic testing,Spartan XC6SLX9 FPGA
更新于2025-09-09 09:28:46
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[IEEE 2017 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC) - Atlanta, GA (2017.10.21-2017.10.28)] 2017 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC) - Pico-TDC: a novel FPGA-based TDC with 2.2ps RMS timing resolution
摘要： The purpose of this work is to develop low-cost high-performance TDCs to meet the requirement from the next generation sub-10ps TOF-PET camera. A TOF-PET system may need hundreds of high resolution TDCs to read timing from many detectors. FPGA-based TDC designs, such as conventional delay-line (DL) TDCs and Wave-Unions (WU) TDCs, are a more viable solutions compared with expensive ASIC-based TDCs. However, the performances of those FPGA-based TDCs are more or less depended on the specific structures and performances of the delay lines, which are usually the carry chains in the adders of a FPGA. In this paper, we present a new method called Pico-TDC method to construct the TDCs in FPGA. The uniqueness of the Pico-TDC method is to use single registers in the FPGA as low-precision TDCs, and to combine many of those low-precision TDCs to construct a high-precision TDC. The advantages of Pico-TDC method are: (1) the timing performance of a Pico-TDC is not limited by the performance of delay lines in the FPGA. As a result, it is possible to achieve unprecedented resolution with a low-cost FPGA. (2) Hundreds of high-performance Pico-TDCs can be constructed in a low-cost FPGA which normally has millions of registers. (3) Theoretically, the Pico-TDCs can be conveniently migrated from one FPGA to another, regardless of the differences in the internal structures of the FPGAs. We have successfully constructed four channels of Pico-TDCs in a low-cost FPGA (Altera Cyclone V 5CEBA4F23C7N, price: $66.63). Each TDC uses 640 registers (low-precision TDCs). The four Pico-TDCs were tested with both the internal and the external pulses. The RMS of the timing measurements is 2.2 ps. The temperature stability is excellent. We conclude that Pico-TDCs have excellent timing performance which meets the requirement of the next generation sub-10ps TOF-PET.
关键词： TDC,TOF-PET,timing resolution,FPGA,Pico-TDC
更新于2025-09-09 09:28:46
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[IEEE 2018 IEEE East-West Design & Test Symposium (EWDTS) - Kazan, Russia (2018.9.14-2018.9.17)] 2018 IEEE East-West Design & Test Symposium (EWDTS) - An FPGA-Optimized Architecture of Variational Optical Flow
摘要： The variational methods for dense optical flow estimation are widely known and adopted techniques for motion detection, object tracking, 3D reconstruction and autonomous navigation image processing applications. A non-linear model of variational optical flow estimation is the most accurate but also most complicated and computationally intensive method and its implementation in an FPGA is compromise from both a design complexity and a performance. The article is devoted to the specific FPGA-based solution which has been implemented using Verilog hardware description language. The suggested solution is able to process the non-linear optical flow in real time and might be applied as FPGA-accelerator for optical flow processing.
关键词： variational methods,optical flow,real-time processing,FPGA,Verilog
更新于2025-09-09 09:28:46
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<b>Compatibility of Anfis controller and FPGA in solar power generation for a domestic oad
摘要： Among other soft computing techniques, the Adaptive Neuro Fuzzy Inference System (Anfis) gives a significant and advantageous result in solar power generation, especially in tracking the maximum power point. Due to the dynamic nature of solar irradiance and temperature, efficient energy conversion is not possible. However, advancements in the areas of artificial intelligence have made it possible to overcome the hurdles. The Maximum Power Point Tracking (MPPT) technique adopting the advantages of Anfis has been proven to be more successful with a fast dynamic response and high accuracy. The complete system is modeled using Matlab/Simulink; the hardware results are validated with the benefits of Field Programmable Logic Array (FPGA) instead of ordinary micro-controllers.
关键词： DC-AC power conversion,MPPT,FPGA,Anfis controller,solar power generation
更新于2025-09-09 09:28:46
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12.3: 4K-UHD 3D Display Processing System Based on FPGA
摘要： BOE 4K-UHD (Ultra-High-Definition, 3840x2160) 3D display processing system based on FPGA (Field Programmable Gate Array) receiving, processing and transmitting of 4K 3D video. In details, 4K 3D video processing functions including interlacing, deinterlacing, stretching, frame rate conversion, mirror image, depth of field adjustment, 2D/3D switching and so on, can be used in the 4K 3D display system. The display system takes advantages of parallel processing architecture based on FPGA device to enhance the ability and efficiency of processing high resolution image, increase the system throughput, which can reach up to 16Gbps, and reduce the system delay, the minimum of which can be within 10ms. Besides, the mainstream video interface protocols including SD/HD/3G-SDI, DisplayPort 1.2, DVI, are realized in FPGA device without the additional protocol conversion chips. This saves space and power. Additionally, the display system supports various 3D formats, including Side-by-Side, Line-by-Line, and Dual-Link. This paper will give a detailed description of the system architecture and key technologies of the display system.
关键词： 3D Display System,FPGA,4K-UHD
更新于2025-09-09 09:28:46
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16.3: Zero Seamless LCD Splice Wall Design System
摘要： LCD splice wall can achieve excellent display result with large area and low cost. The main technology of splice wall include seam width, brightness, contrast, visual angle, chromaticity consistency, liquid crystal response time and so on. Among these factors, the seam width is the most important key affecting the user experience, Now there are three kinds of technology to optimize the seam width: Design more narrow border module, weaken the gap with optical components, weaken the gap with LED. The results of the survey show weaken the gap with LED is the best solution, Filling the gap of LCD splice wall with LED, Through N-Scalar image processing technology, LCD and LED can display the same video at the same time, which can get better display effect. This article focuses on the technical scheme of using LED to weaken the seam, and implemented in one FPGA chip.
关键词： FPGA,LCD splice wall,Splice width,Scalar
更新于2025-09-09 09:28:46