研究目的
Developing a compact silicon-photonic receiver integrated with a 28-nm CMOS transimpedance-amplifier (TIA) chip for high-speed and high-efficiency operation.
研究成果
The developed 5 × 5 mm2 compact silicon-photonic receiver with a CMOS-TIA chip demonstrated 25-Gb/s error-free operation at both 25 and 85 °C. The results show that the receiver can be applied for practical use at high temperatures.
研究不足
The deterministic jitters were relatively large because of the LC resonance between the inductance of the TIA power lines on the platform chip and the parasitic capacitance in the TIA chip.
1：Experimental Design and Method Selection:
The receiver chip was designed using a photonics—electronics convergence design technique. Optical pins were used for easy optical alignment between the multimode fibers and the germanium photodetectors. An aluminum stripline between the PD and the TIA was used to enhance the 3-dB bandwidth. Coplanar waveguides (CPWs) on the etched SOI wafer were used to achieve a low insertion loss.
2：Sample Selection and Data Sources:
The study used a fabricated 5 × 5 mm2 chip-scale optical I/O core receiver integrated with a CMOS-TIA chip.
3：List of Experimental Equipment and Materials:
The receiver consisted of optical pins, Ge-PDs with cathode/anode lines, a TIA-IC, and signal lines on the silicon-photonic platform chip.
4：Experimental Procedures and Operational Workflow:
The receiver characteristics were evaluated through eye-diagram measurements and jitter analysis using a sampling oscilloscope. The BERs of the receiver were tested using an error detector.
5：Data Analysis Methods:
The performance of the receiver was analyzed based on the measured eye diagrams, jitter analysis, and BER tests.
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