研究目的
Investigating the fabrication of large area integrated top-gate nMISFETs with sputter-deposited-MoS2 film for industrial chip-level LSIs.
研究成果
The integration of top-gate MoS2 nMISFETs using sputtering, H2S annealing, and ALD-Al2O3 passivation is a substantial first step towards realizing integrated circuits with 2D materials. Improvements in mobility and contact resistance are necessary for future applications.
研究不足
The mobility of sputtered MoS2 film is lower than those using exfoliation and CVD methods. The contact resistance between MoS2 and TiN is high, and the off current increases with drain voltage.
1：Experimental Design and Method Selection:
The study employs RF sputtering for MoS2 film deposition, H2S annealing for sulfur compensation, and ALD-Al2O3 for passivation.
2：Sample Selection and Data Sources:
MoS2 film of 3-nm thick was deposited on SiO2/Si substrate.
3：List of Experimental Equipment and Materials:
RF sputtering system, ALD system for Al2O3 deposition, TEM, EDX, STEM for structural evaluation.
4：Experimental Procedures and Operational Workflow:
MoS2 deposition, H2S annealing, ALD-Al2O3 passivation, TiN top-gate patterning by RIE.
5：Data Analysis Methods:
Device simulation using TCAD simulator 'Atlas' of Silvaco for threshold voltage analysis.
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