研究目的
To study the feasibility of high-temperature (high-T) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm FDSOI CMOS technology and to explore their scalability through simulation to 2nm dimensions.
研究成果
The paper demonstrates that monolithic integration of qubits and high-fidelity readout circuitry is possible at 2 K in production 22nm FDSOI CMOS technology. Higher temperature operation will be possible with continued scaling of transistor minimum feature size.
研究不足
The operation of the qubits is currently restricted to temperatures below 100 mK due to low confinement and coupling energies. The lack of monolithic integration further degrades readout fidelity and computing speed.
1：Experimental Design and Method Selection:
The study involves the characterization of 22nm FDSOI CMOS technology for quantum computing ICs, focusing on the integration of qubits and electronics on the same die.
2：Sample Selection and Data Sources:
Fabricated transistors, qubits, TIAs, and qubit-with-TIA circuits in a production 22nm FDSOI technology.
3：List of Experimental Equipment and Materials:
Lake Shore CPX VLT system for on-die dc and S-parameter measurements at 300 K and at 2 K.
4：Experimental Procedures and Operational Workflow:
Measurements of minimum-size Si-channel n-MOSFETs, SiGe-channel p-MOSFETs, and double quantum-dot complementary qubits at cryogenic temperatures.
5：Data Analysis Methods:
Analysis of resonant tunneling characteristics and performance metrics of the integrated circuits.
独家科研数据包，助您复现前沿成果，加速创新突破
获取完整内容
