研究目的
To provide a rigorous analysis of phase noise in CMOS ring oscillators, improving on Abidi’s classical study as well as on Homayoun and Razavi’s.
研究成果
Phase noise equations for the inverter-based CMOS ring oscillator have been obtained from a rigorous theoretical analysis. Although derived under specific design conditions, numerical simulations show that they are capable of capturing the phase noise behaviors of CMOS ring oscillators under a wide variety of process parameter values and design choices.
研究不足
The analysis assumes a very high nMOS/pMOS threshold voltage |Vt| with respect to the supply voltage Vdd, which is not the case in most practical applications. However, the derived phase noise equations are still capable of an excellent accuracy, even when |Vt| ? Vdd.
1：Experimental Design and Method Selection:
The study relies on the well-known impulse sensitivity function (ISF) theory, supplemented by a technique borrowed from Abidi’s study to account for the impact of sampled thermal noise. The analysis assumes a very high nMOS/pMOS threshold voltage |Vt| with respect to the supply voltage Vdd.
2：Sample Selection and Data Sources:
The ring oscillator under study is made of an odd number M of identical CMOS inverters, each loaded by a capacitance C.
3：List of Experimental Equipment and Materials:
MOS devices described in Verilog-A language and commercial 55-nm BiCMOS technology.
4：Experimental Procedures and Operational Workflow:
Numerical simulations using spectreRF periodic steady-state (PSS) simulation run on the ring oscillator.
5：Data Analysis Methods:
The phase noise equations are thoroughly tested through numerical simulations.
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