研究目的
To protect integrated circuits (ICs) from malicious attacks by encrypting and obfuscating the IP design using polymorphic logic gates designed with silicon nanowire field effect transistors (SiNW FETs) to reduce performance overhead and preserve the robustness of logic locking techniques.
研究成果
The paper demonstrates that the usage of emerging transistor technology, i.e., SiNW FETs, can improve the logic locking design by preserving lower power and area consumption compared to conventional CMOS technology. A smart placement algorithm achieves 50% Hamming distance between correct and wrong output bits, indicating robust security. The research suggests that security can serve as a new criterion for evaluating emerging devices and anticipates more research outcomes in this area.
研究不足
The paper does not explicitly mention specific limitations of the research. However, potential areas for optimization could include further reducing the performance overhead and enhancing the security against more sophisticated attacks.
1：Experimental Design and Method Selection:
The paper leverages the unique property of emerging transistor technology, specifically SiNW FETs, to design polymorphic logic gates for logic encryption. The methodology includes theoretical analysis and security evaluation of the proposed technique.
2：Sample Selection and Data Sources:
The effectiveness of the proposed technique is evaluated using combinational benchmark circuits from ISCAS’85 benchmark suites.
3：List of Experimental Equipment and Materials:
Synopsys Hailey Simulation Program with Integrated Circuit Emphasis (HSPICE) for circuit simulation, Synopsys Design Compiler for performance overhead evaluation, and Java language for implementing the logic locking algorithm.
4：Experimental Procedures and Operational Workflow:
The process involves designing and simulating SiNW based polymorphic logic gates, implementing the logic locking algorithm, applying random input patterns to the encrypted netlist, and evaluating the performance overhead.
5：Data Analysis Methods:
The security of the logic locking is evaluated based on Hamming distance metrics, and the performance overhead is assessed in terms of area and power-delay product (PDP).
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