1：Experimental Design and Method Selection:

The study employs a 3D monolithic integration approach using inkjet and dispenser printing to fabricate dual-gate organic transistors on flexible plastic substrates. The design includes vertical stacking of complementary transistors with shared gate electrodes to increase density and performance.

2：Sample Selection and Data Sources:

Devices are fabricated on 125 μm-thick polyethylene naphthalate (PEN) films. Materials include organic semiconductors (n-type TU-3 and p-type DTBDT-C6), Ag-nanoparticle ink, Parylene dielectrics, and fluoropolymer banks.

3：List of Experimental Equipment and Materials:

Inkjet printer (DMP 2831, Fujifilm Dimatix), dispenser for printing, chemical vapor deposition for Parylene, semiconductor parameter analyzer (Keithley 4200-SCS), oscilloscope (Tektronix DPO2024B), stylus profiler (Bruker Dektak XT), LCR meter (NF Corporation ZM2376).

4：6). Experimental Procedures and Operational Workflow:

4. Experimental Procedures and Operational Workflow: Sequential printing of metal layers, deposition of dielectric layers, printing of semiconductor inks within hydrophobic banks, thermal annealing, and electrical characterization. Steps include inkjet printing of electrodes, CVD of Parylene, SAM treatment for work function modification, and interconnection via laser-drilled vias.

5：Data Analysis Methods:

Electrical characteristics are measured using semiconductor parameter analyzers. Carrier mobilities are extracted from saturation regime transfer characteristics. Statistical analysis includes standard deviations for uniformity assessment.