研究目的
To propose a new technique for adjusting the duty cycle in a low cost high frequency charge/discharge CMOS oscillator while maintaining low frequency variation over a supply voltage range.
研究成果
The proposed circuit provides an effective duty cycle trimming technique using two bias currents, reducing frequency spread by half compared to oscillators without duty cycle control. It maintains low sensitivity to supply voltage variations. Future work could involve trimming the reference current to counteract frequency lowering for non-50% duty cycles and improving layout symmetry.
研究不足
The circuit has increased current consumption due to added biasing circuitry (about 20uA, 25% of total). Frequency is lowered for duty cycles different from 50%, and nonlinearity may occur. Symmetry and matching in layout are critical to avoid increased variation. The technique is hard to achieve for high-speed circuitry requiring synchronized current changes.
1：Experimental Design and Method Selection:
The study involves designing and simulating a CMOS oscillator circuit using Cadence design suite. The method includes using different bias currents for each stage to adjust duty cycle and analyzing frequency and duty cycle variations over a supply voltage range of 1.6V to 2V. Theoretical models based on capacitor charging and discharging delays are employed.
2：6V to 2V. Theoretical models based on capacitor charging and discharging delays are employed.
Sample Selection and Data Sources:
2. Sample Selection and Data Sources: The circuit is implemented in a low voltage technology with a feature size lower than 0.5um. Simulations are conducted to generate data on frequency and duty cycle for various trimming settings.
3：5um. Simulations are conducted to generate data on frequency and duty cycle for various trimming settings.
List of Experimental Equipment and Materials:
3. List of Experimental Equipment and Materials: Cadence design suite for simulation; CMOS technology with feature size <0.5um; specific components include PMOS and NMOS transistors, capacitors, and inverters as part of the oscillator design.
4：5um; specific components include PMOS and NMOS transistors, capacitors, and inverters as part of the oscillator design.
Experimental Procedures and Operational Workflow:
4. Experimental Procedures and Operational Workflow: The circuit schematic is designed with bias trimming circuitry. Simulations are run for different duty cycle settings (trimming values from 0 to 63) and supply voltages (1.6V, 1.8V, 2V). Data on frequency and duty cycle are collected and analyzed.
5：6V, 8V, 2V). Data on frequency and duty cycle are collected and analyzed.
Data Analysis Methods:
5. Data Analysis Methods: Data is analyzed to compute frequency variation and duty cycle variation percentages. Equations from the paper (e.g., equations 16, 17, 18) are used to model and compare simulated results with theoretical predictions.
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