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- 摘要
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[IEEE 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Porto, Portugal (2018.10.10-2018.10.12)] 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Implementation of a Real-Time Image-Based Vibration Detection and Adaptive Filtering on an FPGA
摘要： In this paper, we propose and implement a field-programmable gate array (FPGA) system which extracts a vibration component of a desired frequency band from moving images in real-time, aiming at application to image-based vibration suppression such as microsurgery assistance systems. The technical challenges to this end are two-fold: fast and robust detection of vibration components in given moving images and zero-phase band-pass filtering for a desired frequency band. For the former, we employ a statistical approach using dense optical flow to derive frequency components, and design a custom optical flow computing hardware with the Lucas-Kanade (LK) method. For the latter, we implement a sort of adaptive band-pass filters called a bandlimited multiple Fourier linear combiner (BMFLC), which can recompose input signals as a mixture of sinusoidal signals with multiple frequencies in a band with no phase delay. Both designs are implemented in a deeply pipelined manner on a Xilinx Kintex-7 XC325T FPGA, without using any external memories. Empirical experiments reveal that the proposed system extracts a vibration component of high-frequency tremors in hand motions, while intentional low-frequency motions are successfully filtered out. The system processes VGA moving images at 60 fps, with a delay of less than 1 us for the BMFLC, suggesting effectiveness of the deep pipelined architecture.
关键词： FPGA,optical flow,real-time image processing,adaptive filtering,vibration detection
更新于2025-09-23 15:22:29
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[IEEE 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Porto, Portugal (2018.10.10-2018.10.12)] 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Real-Time Implementation of Contextual Image Processing Operations for 4K Video Stream in Zynq UltraScale+ MPSoC
摘要： In this paper hardware implementation of selected contextual based image pre-processing modules for a 3840×2160@60fps video stream in a Zynq UltraScale+ MPSoC is discussed. The following operations are considered: simple averaging (box filter), Gaussian filter, edge detection using the Sobel and Canny methods, median filter and morphological erosion and dilation operations. The scheme for implementing contextual based operations for a video stream in the format of 2 and 4 pixels per clock and challenges related to the pipelined implementation of processing such data are described. Also the use of logic resources and energy efficiency of modules described in the Verilog hardware description language and using the High Level Synthesis tools (Vivado HLS, SDSoC and xfOpenCV library) are compared. All designed modules support real-time processing of a 4K@60fps video stream.
关键词： FPGA,Zynq SoC,Canny,Vivado HLS,xfOpenCV,real-time processing,SDSoC,image pre-processing,Sobel,contextual based filtering
更新于2025-09-23 15:22:29
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A High-Level Synthesis Implementation and Evaluation of an Image Processing Accelerator
摘要： Most frequently, an FPGA is used as an implementation platform in applications of graphics processing, as its structure can effectively exploit both spatial and temporal parallelism. Such parallelization techniques involve fundamental restrictions, namely being their dependence on both the processing model and the system’s hardware constraints, that can force the designer to restructure the architecture and the implementation. Predesigned accelerators can significantly assist the designer to solve this problem and meet his deadlines. In this paper, we present our accelerators for Grayscale and Sobel Edge Detection, two of the most fundamental algorithms used in digital image processing projects. We have implemented those algorithms with a “bare-metal” VHDL design, written purely by hand, as a portable USB accelerator device, as well as an HLS-based overlay of a similar implementation designed to be used by a Python interface. The comparisons of the two architectures showcase that the HLS generated design can perform equally to or even better than the handwritten HDL equivalent, especially when the correct compiler directives are provided.
关键词： high level synthesis,FPGA,HDL,python,image processing,accelerator
更新于2025-09-23 15:22:29
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An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy
摘要： In this paper we propose a new algorithm for real-time ?ltering of video sequences corrupted by Poisson noise. The algorithm provides effective denoising (in some cases overcoming the ?ltering performances of state-of-the-art techniques), is ideally suited for hardware implementation, and can be implemented on a small ?eld-programmable gate array using limited hardware resources. The paper describes the proposed algorithm, using X-ray ?uoroscopy as a case study. We use IIR ?lters for time ?ltering, which largely simpli?es hardware cost with respect to previous FIR ?lter-based implementations. A conditional reset is implemented in the IIR ?lter, to minimize motion blur, with the help of an adaptive thresholding approach. Spatial ?ltering performs a conditional mean to further reduce noise and to remove isolated noisy pixels. IIR ?lter hardware implementation is optimized by using a novel technique, based on Steiglitz–McBride iterative method, to calculate ?xed-point ?lter coef?cients with minimal number of nonzero elements. Implementation results using the smallest StratixIV FPGA show that the system uses only, at most, the 22% of the resources of the device, while performing real-time ?ltering of 1024 × 1024@49fps video stream. For comparison, a previous FIR ?lter-based implementation, on the same FPGA, in the same conditions and constraints (1024 × 1024@49fps), requires the 80% of the logic resources of the FPGA.
关键词： Poisson noise,X-ray video?uoroscopy processing,Field-programmable gate array (FPGA),IIR ?ltering,IIR ?lter design,Real-time video ?ltering
更新于2025-09-23 15:22:29
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Hardware implementation of digital image skeletonization algorithm using FPGA for computer vision applications
摘要： This paper proposed a method for digital image skeletonization of 2-D image of size 8 (cid:1) 8 and its implementation on Field Programmable Gate Array (FPGA). The time required to execute the proposed algorithm for 8 (cid:1) 8 dimension image on FPGA recon?gurable hardware is 4.815 ns, maximum output required time after clock: 4.075 ns, maximum frequency: 207.684 MHz, minimum input arrival time before clock: 2.284 ns. These values are for Vertex 5 FPGA board. This proposed algorithm ?nds applications in pattern recognition, computer vision, image matching and so on. This method can used in real time image processing applications. This algorithm may be extended for 3-D images and FPGA architecture may be proposed accordingly.
关键词： Computer vision,Gray scale images,2-D image,Skeleton,FPGA
更新于2025-09-23 15:22:29
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800 nm Bandwidth Amplified Spontaneous Emission of Divalent Cobalt Ion-doped Fiber Pumped at 550 nm
摘要： A fault injection platform which supports both single event upset (SEU) and multiple SEUs for SRAM-based field programmable gate arrays (FPGA) is proposed. The fault injector can inject SEU or accumulated multiple SEUs and repair the SEUs by itself. The proposed fault injection platform is fast because the address generator can generate available value in real time. We show the error rates of the SEU test and multiple SEUs test. The experimental results indicate that SEU has an impact on the sensitivity of design to the next SEU in SRAM-based FPGA.
关键词： multiple SEUs,Fault injection,SEU,SRAM-based FPGA
更新于2025-09-23 15:22:29
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[IEEE 2018 International Conference on Current Trends towards Converging Technologies (ICCTCT) - Coimbatore (2018.3.1-2018.3.3)] 2018 International Conference on Current Trends towards Converging Technologies (ICCTCT) - Generation and Analyzation of Spectral Density for IRNSS SPS PRN Code
摘要： The Indian Regional Navigational Satellite System (IRNSS) satellites provide two services namely standard Positioning Service (SPS) and Restricted Service (RS). L5 and S are the frequency bands from which both the services are utilized. To transmit the navigational information in SPS downlink gold codes are used. Most of the GNSS will work on the principle of CDMA where PRN sequences are the heart of the system. In this paper Pseudo Random Noise (PRN) codes are generated for an SPS signal which is called as SPS PRN code. A CDMA signal is generated using these sequences by using BPSK modulation. The analysis is done based on a time domain signal basis and is used to derive the Power Spectral Density of a CDMA signal. The spectrum analyser optimal operating conditions are observed by using the analytical results. To generate these codes, the polynomials G1 & G2 are selected, which are similar to ones used by GPS C/A signal and are as per the pre-conditions provided in IRNSS_SPS_ICD_June 2014. This paper also covers the process of selection of codes to be computed and the properties of PN-sequence are also analysed. The Xilinx ISE test system and Mat lab apparatus were used for the simulation of SPS PRN codes and additionally the implementation of PRN code is done on FPGA hardware wherein positive results have been obtained. These obtained simulated test results are within the theoretical limits.
关键词： ISE SIMULATOR,FPGA,CDMA,CORRELATION,PRN CODE
更新于2025-09-23 15:22:29
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[IEEE IGARSS 2018 - 2018 IEEE International Geoscience and Remote Sensing Symposium - Valencia (2018.7.22-2018.7.27)] IGARSS 2018 - 2018 IEEE International Geoscience and Remote Sensing Symposium - Near Real-Time Sar Image Focusing Onboard Spacecraft
摘要： SAR imagery requires image focusing through successive signal processing of received data before browsing images and acquiring information. For example, the signal data records of ALOS-2/PALSAR-2 are stored in the onboard mission data storage, transmitted to the ground, and then focused to reproduce images. Apart from the power consumption, the storage volume and the transmission network speed are the two major factors that are limiting the utility of today’s spaceborne SAR systems. One of the solutions is to further compress the SAR data through onboard signal processing and information extraction from the reproduced images. This is also beneficial for event-driven observations and fast delivery of information products. The Emergence Studio of JAXA has been developing evaluation models of FPGA-based signal processing system for onboard SAR image focusing. The model, namely, “Fast L1 Processor 2 (FLIP2)” can reproduce a 3m/6m/10m-resolution single look complex image from ALOS-2/PALSAR-2 data in near real-time. Preliminary evaluation results are presented in this article.
关键词： onboard processing,FPGA,image focusing,SAR
更新于2025-09-23 15:22:29
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LUT-Free Carrier Recovery for Intradyne Optical DPSK Receivers in udWDM-PON
摘要： We present an LUT-free carrier recovery architecture for intradyne optical DPSK receivers that reduces the required DSP hardware resources, power consumption as well as total process clocks, aimed at cost-effective transceivers for access networks applications. The proposed architecture simplifies frequency compensation algorithm to avoid using mth-power operation and LUTs. We prototyped the proposed carrier recovery on a commercial FPGA for real-time evaluation with data at 1.25Gb/s. The optical transmission system is implemented by direct-phase modulation of commercial DFB lasers, 25 km of single-mode fiber, and a coherent receiver with low-cost optical front-end based on 3x3 coupler and three photodiodes providing phase-diversity operation. Results show high performance in real-time, achieving -54 dBm sensitivity at BER = 10-3 as well as feed-forward frequency error correction, high robustness against the fast frequency laser drifts, and high tolerance to optical phase noise in a 6.25GHz spaced ultra-dense WDM grid.
关键词： phase shift keying,FPGA,digital signal processing,Carrier recovery,frequency estimation
更新于2025-09-23 15:22:29
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Time-tagged coincidence counting unit for large-scale photonic quantum computing
摘要： Real-time analysis of single-photon coincidence is critical in photonic quantum computing. The large channel number and high counting rate foreseen in such experiments pose a big challenge for the conventional time tagged method and coincidence instruments. Here we propose a real-time time-tagged coincidence method and a data filtering solution, demonstrated by a 32-channel coincidence counting unit that has been implemented successfully on a field-programmable gate array system. The unit provides high counting rates, a tunable coincidence window, and a timing resolution of 390 ps. Beyond that, it is feasible to be scaled up to 104 channels and is thus ideally suited for channel consuming applications such as boson sampling. Based on the versatility and scalability the unit has shown, we believe that it is the turn-key solution for many single-photon coincidence counting applications in photonic quantum computing.
关键词： boson sampling,FPGA,single-photon coincidence,time-tagged coincidence counting,photonic quantum computing
更新于2025-09-23 15:21:21