研究目的
To develop a low-power low-jitter all-digital phase-locked loop (AD-PLL) in digital sub-sampling architecture which enables multi-bit phase digitization with fine resolution that does not exhibit a strict requirement on its dynamic range for an integer-N operation.
研究成果
The ADC-based AD-PLL (ADC-PLL) is proposed using voltage-domain digitization in sub-sampling architecture. Resolution of phase detection in digital domain can be enhanced by voltage amplification. The voltage domain approach shows the possibility of achieving high resolution in phase digitalization which helps in achieving low in-band phase noise in an AD-PLL.
研究不足
The performance of analog PLLs tends to be limited by device leakage and low supply voltages in highly scaled CMOS technology, causing degradation in integrated phase noise and spur performance.
