研究目的
Investigating the uniform insulating properties of low-temperature curable gate dielectric for organic thin-film transistor arrays on plastic substrate.
研究成果
The cross-linked PHI cured at a low temperature of 130°C exhibited outstanding insulating properties over a large area after the completion of the fabrication process. Based on this result, we successfully fabricated inkjet-printed OTFT arrays on PEN substrates at the low temperature of 130°C, and also demonstrated a 4.8-inch EPD with a high resolution of 98 dpi.
研究不足
The lower mobility of OTFT arrays fabricated on PEN substrate might be attributed to the higher surface roughness of the SiO2 dielectric deposited at low temperature.
1：Experimental Design and Method Selection:
The study proposed a separate evaluation platform to confirm the insulating property of the organic gate dielectric layer after the photolithography process on it. Polymeric gate dielectric composed of poly(hydroxy imide) (PHI) and 2,2'-bis(4-(2-(vinyloxy)ethoxy)phenyl)propane (BPA-DEVE) that can be cured at a low temperature of 130°C was used.
2：Sample Selection and Data Sources:
Thiophene-thiazole-based copolymer semiconductor referred to as P(8T2Z-co-6T2Z)-12 was employed as an active layer.
3：List of Experimental Equipment and Materials:
PHI and BPA-DEVE dissolved in cyclohexanone were spin-coated and cured at 130°C for 10 min on a hot plate to provide a gate dielectric layer with a thickness of 500 nm.
4：Experimental Procedures and Operational Workflow:
Three different devices were fabricated; metal-insulator-metal (MIM) structures on a pristine thin film, evaluation platforms and TFT arrays.
5：Data Analysis Methods:
The leakage current densities were measured for six of the twelve sub regions in the evaluation platform.
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