研究目的
Investigating the fabrication, structure, and electrical properties of epitaxial Cu3Ge thin films for applications in CMOS devices.
研究成果
Epitaxial e1‐Cu3Ge thin films are fabricated on c‐plane sapphire substrate with improved crystallinity. The average work function of epitaxial Cu3Ge thin film is measured to be ～4.47 + 0.02 eV, making it a desirable mid‐gap gate metal for applications in CMOS devices. The presence of twins enhances the mechanical stability and reduces diffusion of Cu and Ge atoms.
研究不足
The study focuses on the fabrication and characterization of epitaxial Cu3Ge thin films on sapphire substrates. Potential areas for optimization include the control of twin density and further reduction of electrical resistivity.
1：Experimental Design and Method Selection:
Pulsed laser deposition (PLD) was used to deposit Ge and Cu thin films repetitively on sapphire substrates. Ultrathin Ge and Cu layers were deposited in each repetition to improve crystallinity.
2：Sample Selection and Data Sources:
A series of five Cu3Ge films are fabricated at 400 ± 10°C, with systematically changed deposition parameters.
3：List of Experimental Equipment and Materials:
High‐resolution transmission electron microscope (HRTEM) JEOL‐2010F, Focus ion beam (FIB), Rigaku X‐ray diffractometer (XRD), Atomic force microscopy (AFM), Kelvin probe force microscopy (KPFM).
4：Experimental Procedures and Operational Workflow:
Multi‐step cleaning of substrates, deposition of Cu and Ge layers, characterization of microstructure and electrical properties.
5：Data Analysis Methods:
XRD θ–2θ scan analysis, HRTEM for microstructure characterization, AFM for morphology, KPFM for work function measurement.
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