研究目的
To present a fully integrated 76-81 GHz FMCW radar transceiver in 65nm CMOS with MIMO processing capabilities, high linearity against TX leakage, and reconfigurable chirp generation.
研究成果
The transceiver achieves 4 GHz FMCW bandwidth, 13.3 MHz/us chirp slope, 13.4 dBm PA output power, and -8.5 dBm RX input PldB with 921 mW power consumption, demonstrating effectiveness for MIMO radar applications with potential improvements through digital signal processing.
研究不足
The center frequency of the receiver is somewhat lower than desired due to inaccurate modeling. The maximum detection range is limited to 20 m due to poor antenna gain.
1：Experimental Design and Method Selection:
The design includes a mixed-mode PLL for chirp generation, high-linearity receivers with passive mixers, and transmitters with Bi-Phase modulation.
2：Sample Selection and Data Sources:
The chip is fabricated in 65nm CMOS technology.
3：List of Experimental Equipment and Materials:
Spectrum analyzer for distance measurement, aluminum foil as target, bond-wires as antennas.
4：Experimental Procedures and Operational Workflow:
The chip is tested for frequency error, output power, noise figure, and real-time distance measurement.
5：Data Analysis Methods:
RMS frequency error calculation, power and noise measurements using standard instrumentation.
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