研究目的
Investigating the effect of semiconductor thickness on the stability of mixed oxide semiconductor thin-film transistors against negative bias combined with light illumination stress, and reducing bias and light instability through an optimized fabrication process.
研究成果
Under an optimized fabrication process with in situ passivation, reducing the semiconductor thickness to around 3 nm significantly reduces bias and light instability in mixed oxide TFTs, achieving negligible threshold voltage shift. This improvement is attributed to a decrease in oxygen-vacancy defects in the bulk, indicating that bulk defects are the primary source of instability. The findings highlight the importance of fabrication process control and suggest that thin semiconductor layers are preferable for stable TFT performance in displays, despite potential trade-offs with on-state current.
研究不足
The study is limited to a specific mixed oxide (a-IGZO) and fabrication process; results may not generalize to other materials or processes. The trade-off between stability and on-state current in thin semiconductor layers could limit practical applications. The experimental conditions (e.g., NBIS stress parameters) are fixed and may not cover all operational scenarios.
1：Experimental Design and Method Selection:
The study uses an optimized fabrication process involving in situ passivation of amorphous indium-gallium zinc-oxide (a-IGZO) layers in a cluster deposition tool without breaking vacuum to minimize contamination. TFTs with varying a-IGZO thicknesses (3-100 nm) are fabricated and characterized for stability under negative bias illumination stress (NBIS).
2：Sample Selection and Data Sources:
Samples are fabricated on glass substrates with Mo gate electrodes, SiO2 gate insulators, and a-IGZO active layers deposited by sputtering. Thicknesses are confirmed via transmission electron microscopy (TEM), and material properties are analyzed using X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS).
3：List of Experimental Equipment and Materials:
Equipment includes sputtering systems for Mo and a-IGZO deposition, plasma-enhanced chemical vapor deposition (PECVD) for SiO2 layers, standard lithography for patterning, TEM for thickness measurement, XRD for crystallinity, XPS for composition, Agilent 4156C semiconductor parameter analyzer for I-V measurements, and Agilent E4980A LCR meter for C-V measurements. Materials include Mo, SiO2, and a-IGZO targets (In2O3:Ga2O3:ZnO = 1:1:1 mol%).
4：Experimental Procedures and Operational Workflow:
The fabrication process involves sequential deposition and patterning steps: gate electrode formation, gate insulator deposition, a-IGZO deposition, back passivation layer deposition (all in vacuum), etch stopper patterning, active island formation, source/drain electrode formation, and final passivation. TFTs are annealed at 250°C in vacuum. NBIS is applied by holding VGS at -20 V for 10,000 s under white light illumination (9000 nit) at room temperature.
5：Data Analysis Methods:
TFT parameters (threshold voltage, field-effect mobility, subthreshold swing) are derived from I-V and C-V characteristics using MOSFET equations. Density of states (DOS) is extracted from combined I-V and C-V analysis. Statistical analysis includes linear regression for trap density estimation.
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semiconductor parameter analyzer
4156C
Agilent
Measuring current-voltage (I-V) characteristics of thin-film transistors.
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LCR meter
E4980A
Agilent
Measuring capacitance-voltage (C-V) characteristics by superimposing gate DC voltage on a small AC signal.
E4980A/E4980AL Precision LCR Meter
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transmission electron microscope
Confirming layer thicknesses of thin-film transistors.
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X-ray diffractometer
Determining crystallinity of IGZO layers.
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X-ray photoelectron spectrometer
Determining chemical composition of IGZO layers.
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sputtering system
Depositing Mo and a-IGZO layers.
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PECVD system
Depositing SiO2 layers as gate insulator and passivation.
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cluster deposition tool
Consecutive deposition of layers without breaking vacuum for in situ passivation.
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